1. Field of the Invention
The present invention relates to semiconductor devices incorporating electrodes consisting of a layer of polysilicon covered by a self-aligned layer of metal silicide.
2. Description of the Related Art
As line widths and geometries for semiconductor devices are made smaller, the polysilicon electrodes that form the gates of MOS devices and wiring lines within semiconductor devices become undesirably resistive. Multilayer electrodes in which a layer of polysilicon is covered by one or more layers of metals or metal suicides are used to provide electrodes having a lower resistance tan electrodes consisting solely of polysilicon. Silicide electrodes may consist, for example, of a layer of polysilicon having a thickness of approximately 1000 .ANG. to 3000 .ANG. covered by titanium silicide to a thickness of greater than 100 .ANG..
A typical implementation of such a multilayer electrode is de so-called self-aligned silicide structure, illustrated in idealized form in FIGS. 1-4. FIGS. 1-4 show cross-sectional views of MOS devices at an early stage of manufacture. The illustrated MOS devices are formed on a P-type substrate 10 and include thick field oxide regions 12 to provide isolation from other, adjacent MOS devices. A gate oxide layer 14, formed by thermal oxidation, covers the active device region of the illustrated device and a polysilicon gate electrode 16 is formed on the gate oxide layer 14. The polysilicon gate electrode 16 is formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), implanting and activating impurities into the polysilicon to render it conductive, and patterning the polysilicon using photolithography. Polysilicon wiring line 18 is formed on the field oxide region 12 at the same time as the gate electrode 16.
Doped source/drain regions 20 are formed on either side of the polysilicon gate electrode to define the channel region of the illustrated MOS transistor. Generally, a lightly doped drain (LDD) structure is used in small design rule MOS transistors of the type that are primarily used in modern memory and logic devices. LDD source/drain regions 20 are typically formed in a two step process, beginning with a relatively low level dopant implantation made self-aligned to a polysilicon gate electrode 16 as illustrated in FIG. 1. Subsequently, spacer oxide regions 22 (FIG. 2) are formed on either side of the gate electrode by first depositing a layer of CVD oxide over the FIG. 1 structure and then anisotropically etching back the oxide layer to expose the substrate over the source/drain regions 20. Etching back the CVD oxide layer produces the spacer oxide regions 22 on either side of the polysilicon gate electrode 16. This process also provides spacer regions 24 on either side of the polysilicon wiring line 18, if the wiring line 18 is exposed during the oxide deposition and etch back process. After the spacer oxide regions 22 are provided on either side of the polysilicon gate electrode 16, a second, heavier ion implantation is made into the source/drain regions 20 self-aligned to the spacer oxide regions 22 (not shown).
The structure illustrated in FIG. 2 includes a polysilicon gate electrode 16 and a polysilicon wiring line 18. For smaller line widths, even highly doped polysilicon is sufficiently resistive to diminish the performance of MOS circuits due to decreased signal levels and longer RC time constants. To reduce the resistance of these gate electrodes and wiring lines, further processing of the FIG. 2 device continues to convert the gate electrode 16 and wiring line 18 into silicide structures using self-aligned silicide (salicide) techniques. Although a variety of different silicides are known to be acceptable, the silicide most commonly used at his time is titanium silicide, and that structure is described herein. Referring now to FIG. 3, silicide lines are formed by first sputtering a layer of titanium over the surface of the device to a thickness of, for example, 500 .ANG.. This titanium layer 26 is converted into titanium silicide at the surface of the polysilicon layers 16, 18 and at the exposed portions of the substrate, including the source/drain regions 20, in a two step process. In the first process step, the device is subjected to a rapid thermal anneal (RTA) by heating the device to a temperature of up to about 700.degree. C. for about thirty seconds, converting the titanium layer 26 into titanium silicide (nominally TiSi.sub.2) where the titanium layer is in contact with a silicon (crystalline or polycrystalline) surface. The device is then etched using a wet etch consisting of H.sub.2 O.sub.2 and NH.sub.4 OH diluted in water, removing unreacted titanium from the surface of the device, exposing the oxide regions of the device. Layers of titanium suicide 30, 32 are left over the polysilicon gate electrode 16 and over the wiring line 18. When the source/drain regions 20 are exposed during the silicidation process, titanium silicide regions 34 are also formed on the surface of the source/drain regions 20. Such titanium silicide regions 34 provide lower sheet resistance over the source/drain regions and provide better contacts to the source/drain regions 20. Titanium silicide contacts on the source/drain regions are thus preferred so long as the amount of silicon consumed in the silicidation process does not alter the gate performance or result in excessive junction leakage at the source/drain regions.
After the unreacted titanium is etched from the device, further processing is necessary to provide suitable self-aligned silicide (salicide) structures for the gate electrodes and wiring lines of the device. The process steps described to this point form a relatively high resistivity phase of titanium silicide on the silicon surfaces, so that the illustrated salicide structure does not have as low of resistivity as is desirable. It is accordingly necessary to expose the device to a second rapid thermal anneal at a temperature in excess of 800.degree. C. for at least ten seconds to convert the titanium silicide to the lower resistivity phase of titanium silicide. The device is then subjected to further processing to complete the fabrication.
A number of the processing steps necessary to the formation of salicide structures are critical. For example, if the temperature control is poor for the initial RTA step of converting the titanium in contact with silicon to titanium silicide, then it is possible that the temperature of the device may get high enough for rapid silicon transport laterally along the titanium layer (26 in FIG. 3), which could convert titanium to titanium silicide in undesirable regions. For example, if silicon is transported along the portion of the titanium layer extending over the oxide spacers 22 on either side of the gate electrode 16, then a "stinger" may be formed bridging between the gate electrode and the source/drain regions 20. Such a stringer 36 bridging between the gate silicide layer 30 and the source/drain silicide region 34 is illustrated in FIG. 5. The formation of the FIG. 5 structure is obviously undesirable in that it shorts the gate to the source/drain region and renders the transistor inoperative.
For smaller device geometries, gate electrodes and wiring lines become narrower and it becomes increasingly more necessary to provide sufficiently low resistivity gate electrodes and wiring lines within memory and logic devices. On the other hand, as narrower gate electrodes and wiring lines are implemented, it is increasingly more difficult to form appropriate salicide electrode structures. In particular, it is difficult to provide the low resistivity phase of titanium silicide for narrow line width gate electrodes and wiring lines. It is accordingly desirable to develop better designs and more robust processing techniques for forming low resistance salicide structures.